IXPUG Asia workshop 2019
Scope
The Intel eXtreme Performance Users Group (IXPUG) is an independent users group whose mission is to provide a forum for the free exchange of information that enhances the usability and efficiency of scientific and technical applications running on large HPC systems using the Intel architecture. IXPUG Workshop Asia 2019 is an open workshop on high performance computing application, system and architectural with Intel technologies. The workshop aims to bring together software developers and technology experts to share challenges, experiences and best‐practice methods for the optimization of HPC, Machine Learning and Data Analytics workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors. The workshop will cover application performance and scalability challenges at all levels – from intra-node performance up to large-scale compute systems. Any research aspect related to Intel HPC products is welcome to present in this workshop.

Note: The workshop is in conjunction with HPC Asia 2019, January 14, 2019, Guangzhou, China
Topics of interest
Any topics on Intel HPC products, including the following topics, but not limited:
● Application porting and performance optimization
● Vectorization, memory, communications, thread and process management
● Multi-node application experiences
● Programming models, algorithms and methods
● Software environment and tools
● Benchmarking and profiling tools
● Visualization development
Submission Guidelines
All submissions will be electronic via Easychair:
https://easychair.org/conferences/?conf=ixpugasia19

Authors are invited to submit technical papers of at most 10 pages (regular paper) or 4 pages (short paper) in PDF format including figures, tables and references. Papers should be formatted in the ACM Proceedings Style which can be got in the following page.
http://www.acm.org/publications/proceedings-template
Important dates
• Submission deadline:  Nov.17, 2018
• Notification of acceptance:  Nov.30, 2018
• Camera-ready final version:  Dec.15, 2018
• Workshop:  Jan.14, 2019
Organizing Chair
James Lin, Shanghai Jiao Tong University
Organizing Co-Chair
Taisuke Boku, University of Tsukuba
Program Committee
• Doug Doerfler (NERSC/LBNL)
• Richard Gerber (NERSC/LBNL)
• Clay Hughes (SNL)
• David Keyes (KAUST)
• Kent Milfeld (TACC)
• Hai Ah Nam (LANL)
• John Pennycook (Intel)
• Thomas Steinke (Zuse Institute Berlin)
• Vit Vondrak (VSB-Technical University of Ostrava)
• Minhua Wen (SJTU)
• Yun Liang (Peking University)
• Tao Wang (Shanghai Supercomputer Center)
• Victor Lee (Intel)
• Zhong Jin (CAS)
Contact
James Lin: james@sjtu.edu.cn
Key Liao: keymorrislane@sjtu.edu.cn
Copyright ©2013 SJTU Network & Information Center All rights reserved.